1. Field
Embodiments of the present invention relate to semiconductor integrated circuits, and more particularly to field effect transistors, and methods for fabricating the transistors.
2. Background Information
A transistor is a semiconductor switching device that may be used to amplify a signal or open or close a circuit. Transistors are important building blocks, along with a few others such as resistors, capacitors, and diodes, to make up logic gates used to create integrated circuits for most electronic devices and computer systems. Modern day microprocessors for computer systems, for example, may contain tens of millions of microscopic transistors. Indeed, it is difficult to imagine that modern computing, as we now know it, would be possible without the use of transistors. Accordingly, the transistor may be regarded among the most significant, important, and valued inventions of the last century.
The inventors have discovered improved transistors and methods for fabricating those transistors. Prior to disclosing the transistors and methods a brief discussion of several prior art transistors may help to illustrate the significance of the developments disclosed herein.
FIG. 1 shows a cross section of a prior art insulated gate field effect transistor 100 having shallow doped extension regions 108A/B from a source 104A and a drain 104B into a channel 110 located beneath an insulated gate 106 such that the extension regions underlap the insulated gate. The transistor is disposed on a silicon substrate 102 and contains the source 104A, the drain 104B, the channel 110, the gate 106, the source extension region 108A from the source into the channel, the drain extension region 108B from the drain into the channel, a gate dielectric 112 to separate the gate from the channel, a source spacer 116A to offset the source from the gate, a source spacer liner 114A to separate the source spacer from the gate, a drain spacer 116B to offset the drain from the gate, and a drain spacer liner 114B to separate the drain spacer from the gate.
The extension regions 108A/B underlap the insulator 112 and the gate 106. The method of fabricating the transistor includes forming the gate dielectric 112 and the gate 106, then forming extension regions 108A/B typically by an ion implantation process that introduces the ions in alignment with the sidewalls of the gate, and then, after forming the extension regions, depositing the source/drain spacer liners 114A/B. Since the doped extension regions are created before the source/drain spacer liners, the location and length of the extension regions (and hence the amount of underlap with the gate) are determined by the sidewalls of the gate, rather than by the sidewalls of the source/drain spacer liners. The underlap may lead to operational problems for the transistor, such as parasitic Miller capacitance that may slow the switching speed of the transistor, and standby or off-state leakage currents.
One approach for reducing the amount of underlap involves forming notches at the base of the gate. FIG. 2 shows a cross-sectional view of a prior art transistor 101 that has notches 118A/B in a notched gate 107 to reduce the underlap of doped extension regions 108A/B with the gate 107. The notches reduce the width at the base of the gate while leaving the width at the top of the gate unaltered. The method of fabricating the transistor includes etching the notches 118A/B from the gate 107 and the gate dielectric 113, then doping extension regions 108A/B by an ion implantation process that introduces the ions at a position of the substrate 102 that is in a vertical line-of-sight alignment with the outermost upper edges of the notched gate, and then (after forming the extension regions) forming source/drain spacer liners 115A/B. The notches reduce the amount of overlap between the gate and the extension regions. Unfortunately, the etching of the notches is difficult to control and the size and shape of the notches may vary and cause variability in the operation of different transistors, which is generally undesirable. Additionally, the notches do not help reduce the width at the top of the notched gate and therefore do not improve the packing density of the transistors in integrated circuits.